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What is a 2nm (N2) process node?

Silicon wafer held by a handling arm inside a semiconductor fabrication chamber
AI-generated editorial illustration · Conceptual scene

A "2nm" node is a chip-manufacturing generation — not a physical measurement of anything on the chip. It is the industry's name for a density and efficiency tier. The IEEE's device-roadmap body (IRDS) said as much in 2020: node numbers such as "5 nm" do not correspond to a meaningful, measurable quantity related to transistor density. TSMC's version, N2, started volume production in Q4 2025.

What actually changed

N2 is TSMC's first generation of nanosheet transistors, a gate-all-around design, and the successor to the FinFET structure that Intel introduced with its 3-D Tri-Gate transistors on the 22nm node, announced in 2011. In general terms, a gate that surrounds the channel more fully controls it better, which is the basis for the gains below.

The figures TSMC quotes (versus its N3E node)

Metric Claim
Performance at the same power +10–15%
Power at the same performance −25–30%
Chip density more than +15%

TSMC stated these figures on its earnings call of July 17, 2025 (the company corrected the low end of the power range to 25% after the call). They are the foundry's figures for the process, not measurements of any finished product.

Why it is in the news

Apple says the A20 Pro in the iPhone 18 Pro, announced on September 9, 2026, is built on a 2-nanometer process; the announcement does not name the foundry. When a launch says "built on 2nm," the claim underneath it is a new transistor structure and, by TSMC's own N2 figures, either 25–30% less power at the same speed or 10–15% more speed at the same power.

Sources

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